CPU core generation for hardware-software codesign

We propose a systematic method which synthesizes the data path and control path of CPU Core from the instruction sequence compiled and translated from C language description of target algorithm in hardware-software codesign environment. We use a graphical representation method to describe instructions in register transfer level. To explore design space more broadly, we apply synthesis parameters selectively, which change the architecture of data path. The number of data transfer paths is reduced by replacing the rarely used path with its bypass route. To select the best among the candidate CPU cores, the data path cost and control path cost are synthesized together.