采用优化的全加法器单元的BEC和FZF逻辑的CSA性能分析

Shivendra Pandey, A. Khan, Jyotirmoy Pathak, R. Sarma
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引用次数: 2

摘要

本文介绍了采用二进制过一变换器(BEC)和第一寻零(FZF)逻辑实现技术的进位选择加法器(CSA)的实现和比较,并通过最小化晶体管数量来优化全加法器(FA)单元。对上述两种逻辑风格在28T、10T和8T FA单元中的实现结果进行了分析和比较,同时对所有三个加法器单元保持用于实现基于BEC和FZF的CSA的所有其他基本单元相同。分析表明,使用FZF逻辑的CSA在所有三个FA单元的功耗和功率延迟积(PDP)方面都更好,而基于BEC的CSA在用于实现整个电路的晶体管数量方面表现更好。所有设计均在Cadence Virtuoso环境下实现1.8伏电源和180nm CMOS工艺技术。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Performance analysis of CSA using BEC and FZF logic with optimized full adder cell
This paper shows the implementation and comparison of Carry Select Adder (CSA) using BEC (Binary Excess one Converter) and First Zero Finding (FZF) logic implementation techniques with optimization of the Full Adder (FA) cell by minimize number of transistors. The results have been analyzed and compared for implementation of both the above logic styles for 28T, 10T and 8T FA cells where as keeping all other basic cells used for implementation of BEC and FZF based CSA same for all three of adder cells. The analysis shows that the CSA using FZF logic is better in terms of power consumption and Power Delay Product (PDP) for all three FA cells however BEC based CSA proves to be better in terms of number of transistors used to implement the overall circuit. All the designs are implemented 1.8Volt power supply and 180nm CMOS process technology in Cadence Virtuoso environment.
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