SurfNoC:一种低延迟且可证明无干扰的芯片网络安全方法

Hassan M. G. Wassel, Ying Gao, J. Oberg, Ted Huffmire, R. Kastner, F. Chong, T. Sherwood
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引用次数: 136

摘要

随着多核处理器越来越多地应用于航空航天和医疗设备等领域,这些领域的故障可能是灾难性的,强大的性能隔离和安全性成为一流的设计约束。当内核用于运行系统的不同部分时,强大的时间和空间分区可以帮助提供这样的保证。但是,随着分区数量的增加或分区带宽分配的不对称,网络时间复用所带来的额外延迟会显著影响性能。在本文中,我们介绍了SurfNoC,这是一种片上网络,可以显着减少时间分区带来的延迟。通过仔细地将网络调度成流经互连的波,这些波携带的来自不同域的数据严格不受干扰,同时避免了与周期时间复用相关的显著开销。我们描述了调度策略和所需的路由器微架构变化,并通过门级信息流分析评估了可合成实现的信息流安全性。在对不同数量的域和网络大小的方法进行比较时,我们发现在许多情况下,SurfNoC可以将实现周期级不干扰的延迟开销减少高达85%。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
SurfNoC: a low latency and provably non-interfering approach to secure networks-on-chip
As multicore processors find increasing adoption in domains such as aerospace and medical devices where failures have the potential to be catastrophic, strong performance isolation and security become first-class design constraints. When cores are used to run separate pieces of the system, strong time and space partitioning can help provide such guarantees. However, as the number of partitions or the asymmetry in partition bandwidth allocations grows, the additional latency incurred by time multiplexing the network can significantly impact performance. In this paper, we introduce SurfNoC, an on-chip network that significantly reduces the latency incurred by temporal partitioning. By carefully scheduling the network into waves that flow across the interconnect, data from different domains carried by these waves are strictly non-interfering while avoiding the significant overheads associated with cycle-by-cycle time multiplexing. We describe the scheduling policy and router microarchitecture changes required, and evaluate the information-flow security of a synthesizable implementation through gate-level information flow analysis. When comparing our approach for varying numbers of domains and network sizes, we find that in many cases SurfNoC can reduce the latency overhead of implementing cycle-level non-interference by up to 85%.
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