并行动态逻辑(PDL)与速度增强倾斜静态(SSS)逻辑

Chulwoo Kim, Seong-ook Jung, K. Baek, S. Kang
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引用次数: 5

摘要

本文描述了一种高速且无电荷共享问题的并行动态逻辑(PDL)。PDL仅使用并联晶体管进行逻辑评估,是高速低压操作的理想选择。与其他使用堆叠晶体管的逻辑方式相比,它具有更小的反向偏置效应。此外,PDL不需要信号排序,也不需要锥形。具有速度增强的倾斜静态逻辑的PDL提供了直接的逻辑合成,而没有由于逻辑重复而造成的面积损失。我们在使用0.25 /spl mu/m CMOS技术的两个32位进位前置加法器上的实验结果表明,具有速度增强的倾斜静态(SSS)逻辑的PDL比时钟延迟(CD)多米诺骨牌的性能提高了15-27%,功率延迟提高了20-37%。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Parallel dynamic logic (PDL) with speed-enhanced skewed static (SSS) logic
In this paper, we describe parallel dynamic logic (PDL) which exhibits high speed and no charge sharing problem. PDL uses only parallel-connected transistors for logic evaluation and is a good candidate for high-speed low-voltage operation. It has less back-bias effect compared to other logic styles which use stacked transistors. Furthermore, PDL needs no signal ordering nor tapering. PDL with speed-enhanced skewed static logic renders straightforward logic synthesis without area penalty due to logic duplication. Our experimental results on two 32-bit carry look ahead adders using 0.25 /spl mu/m CMOS technology showed that PDL with speed-enhanced skewed static (SSS) logic improves performance over clock-delayed (CD)-domino by 15-27% and power delay by 20-37%.
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