Shaked Flur, Susmit Sarkar, Christopher Pulte, Kyndylan Nienhuis, Luc Maranget, Kathryn E. Gray, A. Sezgin, Mark Batty, Peter Sewell
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引用次数: 33
摘要
以前关于轻松共享内存并发性语义的工作只考虑了每次加载只读取一个存储的数据的情况。然而,在实践中,多处理器支持混合大小的访问,这些由系统软件使用,并且(在某种程度上)在C/ c++语言级别上公开。因此,软件的语义基础必须解决这些问题。我们研究了ARMv8和IBM POWER架构和实现的混合大小行为:通过实验,通过开发语义模型,通过测试它们之间的对应关系,以及通过与ARM和IBM员工的讨论。事实证明,这是非常微妙的,在这个过程中,我们必须重新审视连贯性和顺序一致性的基本概念,它们在这个背景下发生了变化。特别是,我们展示了在每个指令之间添加内存屏障并不能恢复顺序一致性。我们继续扩展C/ c++ 11模型,以支持非原子混合大小的内存访问。这是实现真实世界共享内存并发代码语义的必要步骤,超出了石蕊测试。
Mixed-size concurrency: ARM, POWER, C/C++11, and SC
Previous work on the semantics of relaxed shared-memory concurrency has only considered the case in which each load reads the data of exactly one store. In practice, however, multiprocessors support mixed-size accesses, and these are used by systems software and (to some degree) exposed at the C/C++ language level. A semantic foundation for software, therefore, has to address them. We investigate the mixed-size behaviour of ARMv8 and IBM POWER architectures and implementations: by experiment, by developing semantic models, by testing the correspondence between these, and by discussion with ARM and IBM staff. This turns out to be surprisingly subtle, and on the way we have to revisit the fundamental concepts of coherence and sequential consistency, which change in this setting. In particular, we show that adding a memory barrier between each instruction does not restore sequential consistency. We go on to extend the C/C++11 model to support non-atomic mixed-size memory accesses. This is a necessary step towards semantics for real-world shared-memory concurrent code, beyond litmus tests.