管理模拟设计中的过程差异

E. Atwood
{"title":"管理模拟设计中的过程差异","authors":"E. Atwood","doi":"10.1109/TEST.2012.6401527","DOIUrl":null,"url":null,"abstract":"Methods to manage the effect of process normal and process variance on analog circuit designs have driven significant invention within the analog design community. Has test kept up with ensuring outgoing quality? The application of digital algorithms, which control various types of trimming devices, has enabled built in self-calibration (BISC) of sophisticated analog functions. High speed serial applications, phase locked loops, analog-to-digital converters, low voltage amplifiers and digital radios all benefit from improvements to their respective signal-to-noise ratios. In the very large scale integrated digital design space, embedded analog monitors are used to support optimization of power-performance metrics by adjustments to clock tree timing, power supply domain voltage adjustments and circuit redundancy. Memories benefit from redundancy and are a true mixed signal analog design, relying on sophisticated sense amplifiers. All integrated circuits are based on analog circuit behaviors influenced by process variance. Analog functions continue to be specification tested, which has it's own unique coverage issues, but what about the supporting digital circuitry, analog calibration circuitry and redundant logic circuitry? “Who is watching the watchers?” How often is calibration circuitry used? Calibration and redundant circuitry are subject to aging and reliability issues. What needs to be considered in managing these issues? Can useful process feedback information be developed from manufacturing test use of BISC results? Are some calibrations required to be traceable to a standard? How is the relationship managed between analog designers and manufacturing test? Are test access port standards exploited or are ad-hoc access methods used? What can be done to improve the engineering design automation (EDA) environment? Panelists will be asked to present a specific application (case study.) The case study should describe the EDA environment, design/test development flow, the method of BISC or other tuning application and finally manufacturing test application and coverage. Panelists will each be asked to provide an “axiom” intended to provide guidance to engineers working in the area of calibration.","PeriodicalId":6403,"journal":{"name":"2007 IEEE International Test Conference","volume":"6 1","pages":"1"},"PeriodicalIF":0.0000,"publicationDate":"2012-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"\\\"Managing process variance in analog designs\\\"\",\"authors\":\"E. Atwood\",\"doi\":\"10.1109/TEST.2012.6401527\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Methods to manage the effect of process normal and process variance on analog circuit designs have driven significant invention within the analog design community. Has test kept up with ensuring outgoing quality? The application of digital algorithms, which control various types of trimming devices, has enabled built in self-calibration (BISC) of sophisticated analog functions. High speed serial applications, phase locked loops, analog-to-digital converters, low voltage amplifiers and digital radios all benefit from improvements to their respective signal-to-noise ratios. In the very large scale integrated digital design space, embedded analog monitors are used to support optimization of power-performance metrics by adjustments to clock tree timing, power supply domain voltage adjustments and circuit redundancy. Memories benefit from redundancy and are a true mixed signal analog design, relying on sophisticated sense amplifiers. All integrated circuits are based on analog circuit behaviors influenced by process variance. Analog functions continue to be specification tested, which has it's own unique coverage issues, but what about the supporting digital circuitry, analog calibration circuitry and redundant logic circuitry? “Who is watching the watchers?” How often is calibration circuitry used? Calibration and redundant circuitry are subject to aging and reliability issues. What needs to be considered in managing these issues? Can useful process feedback information be developed from manufacturing test use of BISC results? Are some calibrations required to be traceable to a standard? How is the relationship managed between analog designers and manufacturing test? Are test access port standards exploited or are ad-hoc access methods used? What can be done to improve the engineering design automation (EDA) environment? Panelists will be asked to present a specific application (case study.) The case study should describe the EDA environment, design/test development flow, the method of BISC or other tuning application and finally manufacturing test application and coverage. Panelists will each be asked to provide an “axiom” intended to provide guidance to engineers working in the area of calibration.\",\"PeriodicalId\":6403,\"journal\":{\"name\":\"2007 IEEE International Test Conference\",\"volume\":\"6 1\",\"pages\":\"1\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2012-11-05\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2007 IEEE International Test Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/TEST.2012.6401527\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2007 IEEE International Test Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/TEST.2012.6401527","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0

摘要

管理过程正常和过程变化对模拟电路设计的影响的方法已经在模拟设计界推动了重大的发明。测试是否能保证出厂质量?数字算法的应用,控制各种类型的修整装置,使内置自校准(BISC)复杂的模拟功能。高速串行应用,锁相环,模数转换器,低压放大器和数字无线电都受益于各自信噪比的改进。在非常大规模的集成数字设计空间中,嵌入式模拟监视器用于通过调整时钟树定时、电源域电压调整和电路冗余来支持功率性能指标的优化。存储器受益于冗余,是一种真正的混合信号模拟设计,依赖于复杂的感测放大器。所有集成电路都是基于受工艺变化影响的模拟电路行为。模拟功能继续进行规格测试,这有其独特的覆盖问题,但支持的数字电路,模拟校准电路和冗余逻辑电路呢?“谁在监视守望者?”校正电路的使用频率如何?校准和冗余电路受到老化和可靠性问题的影响。在管理这些问题时需要考虑什么?是否可以从使用BISC结果的制造测试中开发有用的过程反馈信息?是否要求某些校准可追溯到某个标准?如何管理模拟设计人员和制造测试之间的关系?是利用了测试访问端口标准还是使用了特别的访问方法?如何改善工程设计自动化(EDA)环境?小组成员将被要求提出一个具体的应用(案例研究)。案例研究应描述EDA环境,设计/测试开发流程,BISC或其他调优应用的方法,最后是制造测试应用和覆盖范围。每个小组成员将被要求提供一个“公理”,旨在为在校准领域工作的工程师提供指导。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
"Managing process variance in analog designs"
Methods to manage the effect of process normal and process variance on analog circuit designs have driven significant invention within the analog design community. Has test kept up with ensuring outgoing quality? The application of digital algorithms, which control various types of trimming devices, has enabled built in self-calibration (BISC) of sophisticated analog functions. High speed serial applications, phase locked loops, analog-to-digital converters, low voltage amplifiers and digital radios all benefit from improvements to their respective signal-to-noise ratios. In the very large scale integrated digital design space, embedded analog monitors are used to support optimization of power-performance metrics by adjustments to clock tree timing, power supply domain voltage adjustments and circuit redundancy. Memories benefit from redundancy and are a true mixed signal analog design, relying on sophisticated sense amplifiers. All integrated circuits are based on analog circuit behaviors influenced by process variance. Analog functions continue to be specification tested, which has it's own unique coverage issues, but what about the supporting digital circuitry, analog calibration circuitry and redundant logic circuitry? “Who is watching the watchers?” How often is calibration circuitry used? Calibration and redundant circuitry are subject to aging and reliability issues. What needs to be considered in managing these issues? Can useful process feedback information be developed from manufacturing test use of BISC results? Are some calibrations required to be traceable to a standard? How is the relationship managed between analog designers and manufacturing test? Are test access port standards exploited or are ad-hoc access methods used? What can be done to improve the engineering design automation (EDA) environment? Panelists will be asked to present a specific application (case study.) The case study should describe the EDA environment, design/test development flow, the method of BISC or other tuning application and finally manufacturing test application and coverage. Panelists will each be asked to provide an “axiom” intended to provide guidance to engineers working in the area of calibration.
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