ieee754浮点单元的VHDL实现

International Conference on Information Communication and Embedded Systems (ICICES2014) Pub Date : 2014-02-01 DOI:10.1109/ICICES.2014.7033999

Anjana Sasidharan, P. Nagarajan

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引用次数: 8

摘要

IEEE-754规定了计算机编程世界中二进制和十进制浮点运算的交换和算术格式和方法。使用此标准的浮点系统的实现可以完全在软件中完成，也可以在硬件中完成，或者在软件和硬件的任何组合中完成。本课题提出IEEE-754浮点单元的VHDL实现。本文采用VHDL语言实现了包、解包和舍入模式，并进行了仿真验证。

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VHDL implementation of IEEE 754 floating point unit

IEEE-754 specifies interchange and arithmetic formats and methods for binary and decimal floating-point arithmetic in computer programming world. The implementation of a floating-point systemusing this standard can be done fully in software, or in hardware, or in any combination of software and hardware. This project propose VHDL implementation of IEEE-754 Floating point unit. In proposed work the pack, unpack and rounding mode was implemented using the VHDL language and simulation was verified.

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International Conference on Information Communication and Embedded Systems (ICICES2014)

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