Efficient Hardware Implementation of Cube Architecture using Yavadunam Sutra on FPGA

Modern computational devices are in need of efficient and optimized hardware architectures with low power and reduced computational complexity. This work presents an efficient and optimized dedicated cube architecture using the proposed modified Yavadunam Sutra Algorithm of Vedic Mathematics. Hardware implementation results of the proposed Vedic cube architecture for input bit-lengths (4-, 8-, 16- and 32-bit) are presented using Field Programmable Gate Array (FPGA) platform. The proposed cubic architecture on modified Yavadunam Sutra outperforms existing state-of-the-art dedicated cube units in terms of combinational delay and area (No. of four-input/slice LUTs) on a FPGA platform. Comparison results of the proposed dedicated cube architecture with reported Vedic cube architectures are also presented.