T. Burd, Wilson Li, James Pistole, S. Venkataraman, M. McCabe, Timothy Johnson, J. Vinh, Thomas Yiu, M. Wasio, H. Wong, Daryl Lieu, Jonathan White, B. Munger, Joshua Lindner, Javin Olson, S. Bakke, Jeshuah Sniderman, Carson Henrion, Russell Schreiber, Eric Busta, Brett Johnson, Tim Jackson, Aron Miller, Ryan Miller, Matthew Pickett, Aaron Horiuchi, Josef Dvorak, Sabeesh Balagangadharan, Sajeesh Ammikkallingal, Pankaj Kumar
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Zen3: The AMD 2nd-Generation 7nm x86-64 Microprocessor Core
“Zen 3” is the first major microarchitectural redesign in the AMD Zen family of microprocessors. Given the same 7nm process technology as the prior-generation “Zen 2” core [1], as well as the same platform infrastructure, the primary “Zen 3” design goals were to provide: 1) a significant instruction-per-cycle (IPC) uplift, 2) a substantial frequency uplift, and 3) continued improvement in power efficiency. The core complex unit (CCX) consists of 8 “Zen 3” cores, each with a 0.5MB private L2 cache, and a 32MB shared L3 cache. Increasing this from 4 cores and 16MB L3 in the prior generation provides additional performance uplift, in addition to the IPC and frequency improvements. The “Zen 3” CCX shown in Fig. 2.7.1 contains 4.08B transistors in 68mm2, and is used across a broad array of client, server, and embedded market segments.
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