A 121dB DR, 0.0017% THD+N, 8× Jitter-Effect Reduction Digital-Input Class-D Audio Amplifier with Supply-Voltage-Scaling Volume Control and Series-Connected DSM

Class-D audio amplifiers have gradually become standard components in mobile devices, where better audio quality over a wide volume range and higher output power $(\mathrm{P}_{\mathrm{O}\mathrm{U}\mathrm{T}})$ are desired. However, in mobile devices, the $\mathrm{P}_{\mathrm{O}\mathrm{U}\mathrm{T}}$ is limited since Li-ion batteries operate at 3 to 4.2V. To increase $\mathrm{P}_{\mathrm{O}\mathrm{U}\mathrm{T}}$, prior publications [1]–[3] have developed embedded boost converters to regulate boosted supply voltage $\mathrm{V}_{\mathrm{P}\mathrm{V}\mathrm{D}\mathrm{D}}$ to 5V or higher for the Class-D power stage at the expense of efficiency degradation. The top of Fig. 31.3.1 shows a typical digital-input open-loop Class-D audio amplifier, where the boost converter is operated only when high $\mathrm{P}_{\mathrm{O}\mathrm{U}\mathrm{T}}$ is required. The input signal is first multiplied by the digital volume level, and then processed by an interpolator and a delta-sigma modulator (DSM) to achieve a high signal-to-quantization-noise ratio (SQNR). Next, the DSM output is converted into a PWM signal with a 384kHz switching frequency $\mathrm{f}_{\mathrm{S}\mathrm{W},\text{Class}}$) by the PCM-to-PWM converter to drive the power stage. The bottom of Fig. 31.3.1 illustrates the dominant factors of the THD+N in different $\mathrm{P}_{\mathrm{O}\mathrm{U}\mathrm{T}}$ regions. In the $\mathrm{l}\mathrm{o}\mathrm{w}-\mathrm{P}_{\mathrm{O}\mathrm{U}\mathrm{T}}$ region, to achieve a high dynamic range (DR), the DSM loop order should be sufficiently high for more aggressive noise-shaping ability so as to suppress the DSM-shaped quantization noise. However, this tends to overload the DSM's quantizer when the DSM input is close to full scale, resulting in a rapidly increasing THD+N due to the clipping error in the $\text{high}-\mathrm{P}_{\mathrm{O}\mathrm{U}\mathrm{T}}$ region. As such, the maximum $\mathrm{P}_{\mathrm{O}\mathrm{U}\mathrm{T}}$ with THD+N<1 % is decreased, which squanders the boosted $\mathrm{V}_{\mathrm{P}\mathrm{V}\mathrm{D}\mathrm{D}}$. In addition to the DSM-shaped noise, the PCM-to-PWM converter's clock (CLK) jitter noise is more significant when PWM pulses are narrower in the $\mathrm{l}\mathrm{o}\mathrm{w}-\mathrm{P}_{\mathrm{O}\mathrm{U}\mathrm{T}}$ region. As for the $\text{medium}-\mathrm{P}_{\mathrm{O}\mathrm{U}\mathrm{T}}$ region, where the minimum THD+N is usually located, the THD+N is dominated by the Class-D power-stage nonlinearities.