第12次会议概述:DRAM:内存小组委员会

Seung-Jun Bae, W. Spirkl, Leland Chang
{"title":"第12次会议概述:DRAM:内存小组委员会","authors":"Seung-Jun Bae, W. Spirkl, Leland Chang","doi":"10.1109/ISSCC.2018.8310254","DOIUrl":null,"url":null,"abstract":"Demand for high-performance and high-capacity DRAMs is increasing more dramatically than in the past, due to the emergence of new areas such as machine learning, VR and AR. In line with this trend, new innovations with capacities of 16Gb and data-rate speeds of 18Gb/s/pin are introduced this year. These changes are common to high-performance computing, gaming graphics, mobile, and server fields, including artificial intelligence. Two graphics DRAM papers of the next generation GDDR6 standard show a maximum data rate of 16 to 18Gb/s/pin with single-ended signaling, and 16Gb high-density DRAMs in a 10nm process node are introduced in LPDDR4X and DDR4. HBM2 is extended to an 8H stack for 64Gb density while keeping a BW of 341GB/s.","PeriodicalId":6511,"journal":{"name":"2016 IEEE International Solid-State Circuits Conference (ISSCC)","volume":"108 1","pages":"202-203"},"PeriodicalIF":0.0000,"publicationDate":"2018-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Session 12 overview: DRAM: Memory subcommittee\",\"authors\":\"Seung-Jun Bae, W. Spirkl, Leland Chang\",\"doi\":\"10.1109/ISSCC.2018.8310254\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Demand for high-performance and high-capacity DRAMs is increasing more dramatically than in the past, due to the emergence of new areas such as machine learning, VR and AR. In line with this trend, new innovations with capacities of 16Gb and data-rate speeds of 18Gb/s/pin are introduced this year. These changes are common to high-performance computing, gaming graphics, mobile, and server fields, including artificial intelligence. Two graphics DRAM papers of the next generation GDDR6 standard show a maximum data rate of 16 to 18Gb/s/pin with single-ended signaling, and 16Gb high-density DRAMs in a 10nm process node are introduced in LPDDR4X and DDR4. HBM2 is extended to an 8H stack for 64Gb density while keeping a BW of 341GB/s.\",\"PeriodicalId\":6511,\"journal\":{\"name\":\"2016 IEEE International Solid-State Circuits Conference (ISSCC)\",\"volume\":\"108 1\",\"pages\":\"202-203\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2018-02-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2016 IEEE International Solid-State Circuits Conference (ISSCC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISSCC.2018.8310254\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 IEEE International Solid-State Circuits Conference (ISSCC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC.2018.8310254","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0

摘要

由于机器学习、虚拟现实和增强现实等新领域的出现,对高性能和高容量dram的需求比过去急剧增长。与这一趋势相一致,今年推出了容量为16Gb、数据速率为18Gb/s/pin的创新产品。这些变化在高性能计算、游戏图形、移动和服务器领域(包括人工智能)都很常见。新一代GDDR6标准的两篇图形DRAM论文显示,单端信令的最大数据速率为16 ~ 18Gb/s/pin, LPDDR4X和DDR4中引入了10nm制程节点的16Gb高密度DRAM。HBM2扩展到8H堆栈,实现64Gb密度,同时保持341GB/s的BW。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Session 12 overview: DRAM: Memory subcommittee
Demand for high-performance and high-capacity DRAMs is increasing more dramatically than in the past, due to the emergence of new areas such as machine learning, VR and AR. In line with this trend, new innovations with capacities of 16Gb and data-rate speeds of 18Gb/s/pin are introduced this year. These changes are common to high-performance computing, gaming graphics, mobile, and server fields, including artificial intelligence. Two graphics DRAM papers of the next generation GDDR6 standard show a maximum data rate of 16 to 18Gb/s/pin with single-ended signaling, and 16Gb high-density DRAMs in a 10nm process node are introduced in LPDDR4X and DDR4. HBM2 is extended to an 8H stack for 64Gb density while keeping a BW of 341GB/s.
求助全文
通过发布文献求助,成功后即可免费获取论文全文。 去求助
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术官方微信