Real-time image processing with a compact FPGA-based systolic architecture

In this paper, a configurable systolic architecture on a chip for real-time window-based image processing is presented. The architecture was specially designed to implement efficiently, both in performance and hardware resource utilization, window-based image operators under real-time constraints. The computational core of the architecture is a configurable 2D systolic array of processing elements, which can provide throughputs over tenths of Giga Operations per Second (GOPs). The architecture employs a novel-addressing scheme that significantly reduces the memory access overhead and makes explicit the data parallelism at a low temporal storage cost. A specialized processing element, called Configurable Window Processor (CWP), was designed to cover a broad range of window-based image algorithms. The functionality of the CWPs can be modified through configuration registers according to a given application. For a current Field Programmable Gate Array (FPGA) prototype of a 7×7 systolic array, the architecture provides a throughput of 3.16 GOPs at a 60 MHz clock frequency. The processing time for a 7×7 generic window-based image operator on 512×512 gray-level images is 8.35 ms. The implemented window-based image operators include generic image convolution, gray-level image morphology and template matching. According to theoretical and experimental results, the architecture compares favorably with other dedicated architectures in terms of performance and hardware resource utilization.