统计设计方法在低压模拟MOS集成电路中的应用

2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353) Pub Date : 2000-05-28 DOI:10.1109/ISCAS.2000.858702

T. Tarim, M. Ismail

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引用次数: 4

摘要

本文介绍了四mosfet结构和10位分流网络的统计设计。给出了两种电路中晶体管失配效应的定量测量方法。优化了晶体管的W和L值，提高了良率。电路采用MOS晶体管Level-3模型参数，采用MOSIS 2 /spl mu/m工艺制作。实验结果也包括在文中。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Application of a statistical design methodology to low voltage analog MOS integrated circuits

The statistical design of the four-MOSFET structure and the 10-bit current division network is presented in this paper. The quantitative measure of the effect of mismatch between the transistors in both circuits is provided. Optimization of transistor W and L values, and yield enhancement are demonstrated. The circuits are fabricated through the MOSIS 2 /spl mu/m process using MOS transistor Level-3 model parameters. The experimental results are included in the paper.

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2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353)

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