纳米级完全耗尽EJ-SOI无结MOSFET,增强模拟性能

S. C. Wagaj, Snehal R. Mulmane, Y. Chavan, S. Patil
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引用次数: 0

摘要

本文提出了一种制造MOSFET无结器件的新方法。我们正在进行一种非传统的电可变超浅结MOSFET的模拟研究,称为EJ-SOI MOSFET,没有形成实际的源极/漏极。随着mosfet的缩放达到极限,在几纳米的非常小的面积内拥有超浅结变得非常困难。这导致了短通道效应的增加。因此,本文提出了一种新的器件结构,其概念是具有感应虚拟源/漏结。所有的努力都是为了减少传统的EJ-SOI MOSFET的短通道效应,提高模拟性能。我们正在将所提出的结构与具有源/漏结的传统ejj - soi器件的性能进行比较。所提出的结构适用于通道长度为50nm和低于50nm的器件。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Nanoscale fully depleted EJ-SOI junctionless MOSFET for enhanced analog performance
In this paper new approach of making a MOSFET as a junctionless device is proposed. We are representing the simulation study of one of non-traditional electrically variable ultra shallow junction MOSFET called EJ-SOI MOSFET without forming actual source/drain junctions. As scaling of MOSFETs reaching its limits, it become very difficult to have ultrashallow junctions within very small area of few nanometers. This leads to increasing short channel effects. So here a new device structure is proposed with a concept of having induced virtual source/drain junctions. All the efforts are made to reduce short channel effects of conventional EJ-SOI MOSFET and to improve analogue performance. We are comparing the performance of proposed structure with conventional EJ-SOI device, which is having source/drain junctions. The proposed structure is suitable for devices having channel length of 50nm and sub 50nm.
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