S. C. Wagaj, Snehal R. Mulmane, Y. Chavan, S. Patil
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Nanoscale fully depleted EJ-SOI junctionless MOSFET for enhanced analog performance
In this paper new approach of making a MOSFET as a junctionless device is proposed. We are representing the simulation study of one of non-traditional electrically variable ultra shallow junction MOSFET called EJ-SOI MOSFET without forming actual source/drain junctions. As scaling of MOSFETs reaching its limits, it become very difficult to have ultrashallow junctions within very small area of few nanometers. This leads to increasing short channel effects. So here a new device structure is proposed with a concept of having induced virtual source/drain junctions. All the efforts are made to reduce short channel effects of conventional EJ-SOI MOSFET and to improve analogue performance. We are comparing the performance of proposed structure with conventional EJ-SOI device, which is having source/drain junctions. The proposed structure is suitable for devices having channel length of 50nm and sub 50nm.