Multi-Chiplet Placement Design for 3D Integration

The main development trend of modern microelectronics is to continuously reduce product mass and dimension, and also increase their performance and reliability. The wide application of multichiplet architecture in high-performance computing clusters has aroused great interest. The multi-chiplet placement can influence the signal transmission behavior in a 3D integration architecture. Interchip communication has remained a major design factor due to the diverse traffic requirements in heterogeneous multi-chiplet systems. In general, to exploit the capabilities of a multi-chiplet architecture without I/O bottlenecks, dense vertical connections in stacked chips become of increasing importance in modern semiconductor technology. Consider a heterogeneous or homogeneous multi-chiplet architecture with a dense vertical connection system that gains a performance per energy benefit from fast state migration between these chiplets. In this paper, we study the effects of signal transmission on different chiplet placement designs, in which wirelessly connected multi-chiplets modules are proposed. The inter-chip wireless heterogeneous or homogeneous multi-chiplet architecture is modeled using a high-frequency structure simulator, in particular, the placement effect of the side differential vertical signal transmission is analyzed.