{"title":"精确的三通道集成时间计数器","authors":"R. Szplet, P. Kwiatkowski, Z. Jachna, K. Rozyc","doi":"10.1109/FCS.2015.7138910","DOIUrl":null,"url":null,"abstract":"We present a design, FPGA-based implementation and test results of a new three-channel time interval counter developed for a project called Legal Time Distribution System (LTDS). The main aim of the counter is to gather information about time drift of clocks involved into the LTDS, then to evaluate their stability, and finally to select the most stable one as a local clock. The counter provides a high measurement precision (<; 15 ps) and wide range (> 1s) that are obtained by combining period counting with two-stage time interpolation. The time counter is implemented in a universally available and relatively cheap programmable device from family Spartan-6 (Xilinx).","PeriodicalId":57667,"journal":{"name":"时间频率公报","volume":"6 1","pages":"575-578"},"PeriodicalIF":0.0000,"publicationDate":"2015-04-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Precise three-channel integrated time counter\",\"authors\":\"R. Szplet, P. Kwiatkowski, Z. Jachna, K. Rozyc\",\"doi\":\"10.1109/FCS.2015.7138910\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We present a design, FPGA-based implementation and test results of a new three-channel time interval counter developed for a project called Legal Time Distribution System (LTDS). The main aim of the counter is to gather information about time drift of clocks involved into the LTDS, then to evaluate their stability, and finally to select the most stable one as a local clock. The counter provides a high measurement precision (<; 15 ps) and wide range (> 1s) that are obtained by combining period counting with two-stage time interpolation. The time counter is implemented in a universally available and relatively cheap programmable device from family Spartan-6 (Xilinx).\",\"PeriodicalId\":57667,\"journal\":{\"name\":\"时间频率公报\",\"volume\":\"6 1\",\"pages\":\"575-578\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2015-04-12\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"时间频率公报\",\"FirstCategoryId\":\"1089\",\"ListUrlMain\":\"https://doi.org/10.1109/FCS.2015.7138910\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"时间频率公报","FirstCategoryId":"1089","ListUrlMain":"https://doi.org/10.1109/FCS.2015.7138910","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
We present a design, FPGA-based implementation and test results of a new three-channel time interval counter developed for a project called Legal Time Distribution System (LTDS). The main aim of the counter is to gather information about time drift of clocks involved into the LTDS, then to evaluate their stability, and finally to select the most stable one as a local clock. The counter provides a high measurement precision (<; 15 ps) and wide range (> 1s) that are obtained by combining period counting with two-stage time interpolation. The time counter is implemented in a universally available and relatively cheap programmable device from family Spartan-6 (Xilinx).
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