用于1000Base-T千兆以太网的低复杂度联合均衡器和解码器

Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044) Pub Date : 2000-05-21 DOI:10.1109/CICC.2000.852709

E. Haratsch, K. Azadet

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引用次数: 4

摘要

提出了一种用于1000Base-T千兆以太网的低复杂度联合解码与均衡的VLSI架构。一抽头并行决策反馈解码器联合解码栅格并取消由于后光标通道脉冲响应的第一抽头的ISI。一维分支度量以前瞻性的方式预先计算，以满足速度要求。用一个简单的决策反馈预滤波器消除了通道脉冲响应中不太重要的尾部。该设计已在3.3 V, 0.25 /spl mu/m标准单元CMOS工艺下实现，工作频率为125 MHz。

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A low complexity joint equalizer and decoder for 1000Base-T Gigabit Ethernet

A VLSI architecture for low complexity joint decoding and equalization for 1000Base-T Gigabit Ethernet is presented. A one-tap parallel decision-feedback decoder jointly decodes the trellis and cancels the ISI due to the first tap of the post-cursor channel impulse response. The one-dimensional branch metrics are precomputed in a look-ahead fashion to meet the speed requirements. The less significant tail of the channel impulse response is canceled with a simple decision-feedback prefilter. The design has been implemented in 3.3 V, 0.25 /spl mu/m standard cell CMOS process for operation at 125 MHz.

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Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)

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