用于自动模型提取的高级符号仿真

2009 12th International Symposium on Design and Diagnostics of Electronic Circuits & Systems Pub Date : 2009-04-15 DOI:10.1109/DDECS.2009.5012132

F. Ouchet, D. Borrione, K. Morin-Allory, L. Pierre

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引用次数: 11

摘要

本文描述了一个从VHDL描述中提取形式模型的符号模拟器VSYML。生成的模型足以在各种框架中进行形式推理。VSYML是它的祖先Theosim的重新实现;它带来了各种各样的改进，例如，关于数组和其他复杂的数据类型。

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High-level symbolic simulation for automatic model extraction

This paper describes VSYML, a symbolic simulator that extracts formal models from VHDL descriptions. The generated models are adequate to formal reasoning in various frameworks. VSYML is a reimplementation of its ancestor Theosim; it brings various improvements e.g., with regard to arrays and other complex data types.

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2009 12th International Symposium on Design and Diagnostics of Electronic Circuits & Systems

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