采用Sps技术的高效功耗Vlsi架构

2013 International Conference on Emerging Trends in VLSI, Embedded System, Nano Electronics and Telecommunication System (ICEVENT) Pub Date : 2013-04-11 DOI:10.1109/ICEVENT.2013.6496584

S. Ramakrishnan, G. Hemalatha, P. Mohan, R. Seshadri

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引用次数: 1

摘要

在超大规模集成电路中采用杂散功率抑制技术(SPST)可以显著降低系统功耗。这里我们将在无限脉冲响应(IIR)和有限脉冲响应(FIR)滤波器架构中实现此设计。当我们在这个乘法器中使用这种技术时，生成的部分乘积的数量将减少一半，从而减少了计算量。显然，通过使用各种硬件设备，这种方法也降低了功耗。

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Power efficient Vlsi architecture using Sps technique

Using spurious power suppression technique (SPST) in VLSI will reduce the power consumption of the system significantly. Here we are going to implement this design in Infinite Impulse Response (IIR) and Finite Impulse Response (FIR) filter architecture. When we are using this technique in this multipliers the no of partial products generated will be reduced to half which reduces the computation. Then obviously the power consumption is also reduced by this method using the various hardware device.

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来源期刊

2013 International Conference on Emerging Trends in VLSI, Embedded System, Nano Electronics and Telecommunication System (ICEVENT)

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