{"title":"一辆3.2陆地/ c。0.35V 10b 100KS/s SAR ADC, 90nm CMOS","authors":"Hung-Yen Tai, Hung-Wei Chen, Hsin-Shu Chen","doi":"10.1109/VLSIC.2012.6243805","DOIUrl":null,"url":null,"abstract":"A low-voltage energy-efficient SAR ADC is presented in this paper with four techniques. Arbitrary weight capacitor array tolerates errors to reduce conversion time. To operate under low voltage, DAC common mode level shift and leakage reduction sample switch with a charge pump are proposed. Differential control logic is used to save its digital power. The prototype ADC consumes 170nW at 100KS/s from a 0.35V supply. It achieves an SNDR of 56.3dB at Nyquist rate and its FOM is 3.2fJ/c.-s.","PeriodicalId":6347,"journal":{"name":"2012 Symposium on VLSI Circuits (VLSIC)","volume":"38 1","pages":"92-93"},"PeriodicalIF":0.0000,"publicationDate":"2012-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"25","resultStr":"{\"title\":\"A 3.2fJ/c.-s. 0.35V 10b 100KS/s SAR ADC in 90nm CMOS\",\"authors\":\"Hung-Yen Tai, Hung-Wei Chen, Hsin-Shu Chen\",\"doi\":\"10.1109/VLSIC.2012.6243805\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A low-voltage energy-efficient SAR ADC is presented in this paper with four techniques. Arbitrary weight capacitor array tolerates errors to reduce conversion time. To operate under low voltage, DAC common mode level shift and leakage reduction sample switch with a charge pump are proposed. Differential control logic is used to save its digital power. The prototype ADC consumes 170nW at 100KS/s from a 0.35V supply. It achieves an SNDR of 56.3dB at Nyquist rate and its FOM is 3.2fJ/c.-s.\",\"PeriodicalId\":6347,\"journal\":{\"name\":\"2012 Symposium on VLSI Circuits (VLSIC)\",\"volume\":\"38 1\",\"pages\":\"92-93\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2012-06-13\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"25\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2012 Symposium on VLSI Circuits (VLSIC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIC.2012.6243805\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2012 Symposium on VLSI Circuits (VLSIC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.2012.6243805","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 3.2fJ/c.-s. 0.35V 10b 100KS/s SAR ADC in 90nm CMOS
A low-voltage energy-efficient SAR ADC is presented in this paper with four techniques. Arbitrary weight capacitor array tolerates errors to reduce conversion time. To operate under low voltage, DAC common mode level shift and leakage reduction sample switch with a charge pump are proposed. Differential control logic is used to save its digital power. The prototype ADC consumes 170nW at 100KS/s from a 0.35V supply. It achieves an SNDR of 56.3dB at Nyquist rate and its FOM is 3.2fJ/c.-s.
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