Structural decomposition with functional considerations for low power

In this paper we present an approach to minimize power consumption in the logic synthesis stage by using the gate decomposition technique. Since the power consumption of ICs is not only decided by the switching activity of each gate but also depends on the gate types in the target library, the major difference between our algorithm and the traditional methods is that we consider the power consumption of different types of gate. In addition, by the usage of inverter relocation based on Demorgan's law, we can further reduce the IC's total power consumption. Under the cases of different of input signal probabilities, switching rates are applied, and experimental results show that our approach can further reduce average power consumption by up to 12.7% as compared to the case of the applied ExDecomp/HeuDecomp algorithm (Twari et al, Proc. 30th Design Automation Conf., pp.74-79, 1993).