在TX和RX端端电阻均为4×Z0的单端点对点DRAM接口的收发器功率降低27%

2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers Pub Date : 2013-03-28 DOI:10.1109/ISSCC.2013.6487747

Soo-Min Lee, Jong-Hoon Kim, Jongsam Kim, Yunsaing Kim, Hyunbae Lee, J. Sim, Hong-June Park

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引用次数: 9

摘要

在单端点对点DRAM接口中，通过将TX和RX两端的终端电阻增加到4×Z0，可以将收发器功率降低27%。由此产生的ISI和反射的增加在RX处分别通过使用1抽头和2抽头积分决策反馈均衡器(IDFE)进行补偿，其中反射抽头位置和抽头系数在训练模式中自动找到。这将在0.13μm CMOS中以5Gb/s速度将4英寸FR4通道的浴缸开度从20%提高到62.5%。

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A 27% reduction in transceiver power for single-ended point-to-point DRAM interface with the termination resistance of 4×Z0 at both TX and RX

The transceiver power is reduced by 27% in the single-ended point-to-point DRAM interface by increasing the termination resistance to 4×Z0 at both ends of TX and RX. The resultant increase of ISI and reflection is compensated for at RX by using the 1-tap and 2-tap integrating decision-feedback equalizer (IDFE), respectively, where the reflection tap position and the tap coefficients are found automatically during the training mode. This improves the bathtub opening of a 4-inch FR4 channel from 20% to 62.5% at 5Gb/s in 0.13μm CMOS.

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2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers

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