{"title":"单薄盒(SOTB) mosfet中线边缘粗糙度引起的可变性","authors":"Yunxiang Yang, Xiaoyan Liu, G. Du, R. Han","doi":"10.1109/SNW.2010.5562559","DOIUrl":null,"url":null,"abstract":"Statistical 3D TCAD simulations of 20nm gate SOTB MOSFETs have been done to study the effects of TBox, Vback-gate and WF on LER-induced variability. Our results show that thin box, reverse back-gate bias and high WF are effective ways to control the LER-induced threshold voltage's variations, especially for n-SOTB MOSFETs.","PeriodicalId":6433,"journal":{"name":"2010 Silicon Nanoelectronics Workshop","volume":"70 1 1","pages":"1-2"},"PeriodicalIF":0.0000,"publicationDate":"2010-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Variability induced by Line edge roughness in silicon on thin box (SOTB) MOSFETs\",\"authors\":\"Yunxiang Yang, Xiaoyan Liu, G. Du, R. Han\",\"doi\":\"10.1109/SNW.2010.5562559\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Statistical 3D TCAD simulations of 20nm gate SOTB MOSFETs have been done to study the effects of TBox, Vback-gate and WF on LER-induced variability. Our results show that thin box, reverse back-gate bias and high WF are effective ways to control the LER-induced threshold voltage's variations, especially for n-SOTB MOSFETs.\",\"PeriodicalId\":6433,\"journal\":{\"name\":\"2010 Silicon Nanoelectronics Workshop\",\"volume\":\"70 1 1\",\"pages\":\"1-2\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2010-06-13\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2010 Silicon Nanoelectronics Workshop\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SNW.2010.5562559\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2010 Silicon Nanoelectronics Workshop","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SNW.2010.5562559","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Variability induced by Line edge roughness in silicon on thin box (SOTB) MOSFETs
Statistical 3D TCAD simulations of 20nm gate SOTB MOSFETs have been done to study the effects of TBox, Vback-gate and WF on LER-induced variability. Our results show that thin box, reverse back-gate bias and high WF are effective ways to control the LER-induced threshold voltage's variations, especially for n-SOTB MOSFETs.