Plasma damage in HIMOS/spl trade/ non-volatile memories (NVM)

In this paper, for the first time, plasma induced damage (PID) on floating gate based non-volatile memory cells is reported. Since the cells consist of a complex combination of tunnel and gate oxides, combined with a dense frame of metal interconnect, the chance that these cells may be affected by plasma damage is evident. In order to investigate if the plasma damage affects the flash memory cells, the appropriate test structures have been designed, manufactured and measured. The test structures include structures to generate plasma damage as well as possible protective structures to prevent plasma damage.