{"title":"基于基数-16算法的脉冲神经网络指数函数加速器","authors":"Chenxiao Lin, Qingyang Zeng, D. Shang","doi":"10.1587/elex.19.20220393","DOIUrl":null,"url":null,"abstract":"A range reduction method for shift-and-add algorithms for exponential functions is proposed in this paper. An exponential function accelerator with this method and radix-16 shift-and-add algorithm has been implemented in SMIC 55 nm CMOS process. Compared with the existing method, the proposed method reduces the latency (cycles) by 33% and 20% for 16 and 32-bit precision results, respectively; thereby increasing the throughputto50Mexp/sandreducingthepowerconsumptionto4.6pJ/exp.Inaddition,thismethodsavesdieareasincenoarithmeticunitsareadopted.Thisexponentialacceleratorissupposedtobeusedinaneuromorphicchipforspikingneuralnetworkmodeling.","PeriodicalId":13437,"journal":{"name":"IEICE Electron. Express","volume":"101 1","pages":"20220393"},"PeriodicalIF":0.0000,"publicationDate":"2023-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"An exponential function accelerator with radix-16 algorithm for spiking neural networks\",\"authors\":\"Chenxiao Lin, Qingyang Zeng, D. Shang\",\"doi\":\"10.1587/elex.19.20220393\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A range reduction method for shift-and-add algorithms for exponential functions is proposed in this paper. An exponential function accelerator with this method and radix-16 shift-and-add algorithm has been implemented in SMIC 55 nm CMOS process. Compared with the existing method, the proposed method reduces the latency (cycles) by 33% and 20% for 16 and 32-bit precision results, respectively; thereby increasing the throughputto50Mexp/sandreducingthepowerconsumptionto4.6pJ/exp.Inaddition,thismethodsavesdieareasincenoarithmeticunitsareadopted.Thisexponentialacceleratorissupposedtobeusedinaneuromorphicchipforspikingneuralnetworkmodeling.\",\"PeriodicalId\":13437,\"journal\":{\"name\":\"IEICE Electron. Express\",\"volume\":\"101 1\",\"pages\":\"20220393\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2023-01-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEICE Electron. Express\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1587/elex.19.20220393\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEICE Electron. Express","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1587/elex.19.20220393","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
An exponential function accelerator with radix-16 algorithm for spiking neural networks
A range reduction method for shift-and-add algorithms for exponential functions is proposed in this paper. An exponential function accelerator with this method and radix-16 shift-and-add algorithm has been implemented in SMIC 55 nm CMOS process. Compared with the existing method, the proposed method reduces the latency (cycles) by 33% and 20% for 16 and 32-bit precision results, respectively; thereby increasing the throughputto50Mexp/sandreducingthepowerconsumptionto4.6pJ/exp.Inaddition,thismethodsavesdieareasincenoarithmeticunitsareadopted.Thisexponentialacceleratorissupposedtobeusedinaneuromorphicchipforspikingneuralnetworkmodeling.
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