超低功耗CMOS亚阈值电压基准,不需要电阻或bjt

Yang Liu, Chenchang Zhan, Lidan Wang
{"title":"超低功耗CMOS亚阈值电压基准,不需要电阻或bjt","authors":"Yang Liu, Chenchang Zhan, Lidan Wang","doi":"10.1109/APCCAS.2016.7804066","DOIUrl":null,"url":null,"abstract":"This paper presents a novel ultra-low power voltage reference operational from supply voltage down to less than 0.9V. In the proposed reference circuit, the PTAT voltage is generated by feeding the leakage current of a zero-Vgs NMOS transistor to two diode-connected NMOS transistors, both of which are in subthreshold region; while the CTAT voltage is created by using the body-diodes of another NMOS transistor. Consequently, low-voltage, low-power operation can be achieved without requiring resistors or BJTs, hence with small chip area consumption. The proposed circuit is designed in a 0.18-μm process. Simulation results show that it is capable of providing an 808mV reference voltage with 10ppm/°C from −30°C–125°C even with only 900mV supply voltage. Moreover, the typical power consumption is only 10nW.","PeriodicalId":6495,"journal":{"name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"An ultra-low power CMOS subthreshold voltage reference without requiring resistors or BJTs\",\"authors\":\"Yang Liu, Chenchang Zhan, Lidan Wang\",\"doi\":\"10.1109/APCCAS.2016.7804066\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a novel ultra-low power voltage reference operational from supply voltage down to less than 0.9V. In the proposed reference circuit, the PTAT voltage is generated by feeding the leakage current of a zero-Vgs NMOS transistor to two diode-connected NMOS transistors, both of which are in subthreshold region; while the CTAT voltage is created by using the body-diodes of another NMOS transistor. Consequently, low-voltage, low-power operation can be achieved without requiring resistors or BJTs, hence with small chip area consumption. The proposed circuit is designed in a 0.18-μm process. Simulation results show that it is capable of providing an 808mV reference voltage with 10ppm/°C from −30°C–125°C even with only 900mV supply voltage. Moreover, the typical power consumption is only 10nW.\",\"PeriodicalId\":6495,\"journal\":{\"name\":\"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2016-10-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/APCCAS.2016.7804066\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/APCCAS.2016.7804066","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3

摘要

本文提出了一种新颖的超低功率基准电压,可从电源电压降至0.9V以下。在本文提出的参考电路中,通过将零vgs NMOS晶体管的泄漏电流馈送到两个处于亚阈值区域的二极管连接的NMOS晶体管,从而产生PTAT电压;而CTAT电压是通过使用另一个NMOS晶体管的体二极管产生的。因此,无需电阻或bjt即可实现低电压、低功耗操作,因此芯片面积消耗小。该电路采用0.18 μm工艺设计。仿真结果表明,在- 30°C - 125°C范围内,即使电源电压只有900mV,也能提供10ppm/°C的808mV参考电压。此外,典型的功耗仅为10nW。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
An ultra-low power CMOS subthreshold voltage reference without requiring resistors or BJTs
This paper presents a novel ultra-low power voltage reference operational from supply voltage down to less than 0.9V. In the proposed reference circuit, the PTAT voltage is generated by feeding the leakage current of a zero-Vgs NMOS transistor to two diode-connected NMOS transistors, both of which are in subthreshold region; while the CTAT voltage is created by using the body-diodes of another NMOS transistor. Consequently, low-voltage, low-power operation can be achieved without requiring resistors or BJTs, hence with small chip area consumption. The proposed circuit is designed in a 0.18-μm process. Simulation results show that it is capable of providing an 808mV reference voltage with 10ppm/°C from −30°C–125°C even with only 900mV supply voltage. Moreover, the typical power consumption is only 10nW.
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