{"title":"PPRAM的当前状态","authors":"K. Murakami","doi":"10.1109/ICVC.1999.820902","DOIUrl":null,"url":null,"abstract":"The paper outlines the current status of PPRAM-related projects at Kyushu University and other institutes: (1) PPRAM-Link; (2) PPRAM-Link interface IP cores; (3) reference PPRAM architectures; (4) PPRAM-MOE. The paper also discusses two on-chip memory-path architectures for PPRAM-type SOCs in detail: variable line-size cache and way-predicting set-associative cache.","PeriodicalId":13415,"journal":{"name":"ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361)","volume":"52 4 1","pages":"266-276"},"PeriodicalIF":0.0000,"publicationDate":"1999-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Current status of PPRAM\",\"authors\":\"K. Murakami\",\"doi\":\"10.1109/ICVC.1999.820902\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The paper outlines the current status of PPRAM-related projects at Kyushu University and other institutes: (1) PPRAM-Link; (2) PPRAM-Link interface IP cores; (3) reference PPRAM architectures; (4) PPRAM-MOE. The paper also discusses two on-chip memory-path architectures for PPRAM-type SOCs in detail: variable line-size cache and way-predicting set-associative cache.\",\"PeriodicalId\":13415,\"journal\":{\"name\":\"ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361)\",\"volume\":\"52 4 1\",\"pages\":\"266-276\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1999-10-26\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICVC.1999.820902\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICVC.1999.820902","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
The paper outlines the current status of PPRAM-related projects at Kyushu University and other institutes: (1) PPRAM-Link; (2) PPRAM-Link interface IP cores; (3) reference PPRAM architectures; (4) PPRAM-MOE. The paper also discusses two on-chip memory-path architectures for PPRAM-type SOCs in detail: variable line-size cache and way-predicting set-associative cache.