基于PD-SOI CMOS技术的抗辐射SRAM电池设计

2011 IEEE International Conference of Electron Devices and Solid-State Circuits Pub Date : 2011-12-29 DOI:10.1109/EDSSC.2011.6117575

Yiqi Wang, Ying Li, F. Zhao, Mengxin Liu, Zhengsheng Han

{"title":"基于PD-SOI CMOS技术的抗辐射SRAM电池设计","authors":"Yiqi Wang, Ying Li, F. Zhao, Mengxin Liu, Zhengsheng Han","doi":"10.1109/EDSSC.2011.6117575","DOIUrl":null,"url":null,"abstract":"A miller MOS capacitor in PD-SOI process is introduced between the internal latch nodes of six transistor cells to improve SEU (Single Event Upset) immunity of SRAM cells. SPICE analysis of SEU sensitivity of proposed 6-T SRAM cell, which bases on device-physics-basic SPICE model in 0.35µm PD-SOI CMOS technology, indicates that the upset threshold of the proposed cell can reach to 36fC and increases by 33.3% than 6T without miller capacitor.","PeriodicalId":6363,"journal":{"name":"2011 IEEE International Conference of Electron Devices and Solid-State Circuits","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A radiation hardened SRAM cell design in PD-SOI CMOS technology\",\"authors\":\"Yiqi Wang, Ying Li, F. Zhao, Mengxin Liu, Zhengsheng Han\",\"doi\":\"10.1109/EDSSC.2011.6117575\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A miller MOS capacitor in PD-SOI process is introduced between the internal latch nodes of six transistor cells to improve SEU (Single Event Upset) immunity of SRAM cells. SPICE analysis of SEU sensitivity of proposed 6-T SRAM cell, which bases on device-physics-basic SPICE model in 0.35µm PD-SOI CMOS technology, indicates that the upset threshold of the proposed cell can reach to 36fC and increases by 33.3% than 6T without miller capacitor.\",\"PeriodicalId\":6363,\"journal\":{\"name\":\"2011 IEEE International Conference of Electron Devices and Solid-State Circuits\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2011-12-29\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2011 IEEE International Conference of Electron Devices and Solid-State Circuits\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EDSSC.2011.6117575\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2011 IEEE International Conference of Electron Devices and Solid-State Circuits","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EDSSC.2011.6117575","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 0

摘要

为了提高SRAM单元的抗单事件干扰能力，在6个晶体管单元的内部锁存节点之间引入了PD-SOI工艺中的miller MOS电容。基于0.35µm PD-SOI CMOS技术中器件物理-基本SPICE模型的6-T SRAM电池的SEU灵敏度SPICE分析表明，该电池的扰动阈值可达到36fC，比未使用米勒电容器的6T提高了33.3%。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

A radiation hardened SRAM cell design in PD-SOI CMOS technology

A miller MOS capacitor in PD-SOI process is introduced between the internal latch nodes of six transistor cells to improve SEU (Single Event Upset) immunity of SRAM cells. SPICE analysis of SEU sensitivity of proposed 6-T SRAM cell, which bases on device-physics-basic SPICE model in 0.35µm PD-SOI CMOS technology, indicates that the upset threshold of the proposed cell can reach to 36fC and increases by 33.3% than 6T without miller capacitor.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

2011 IEEE International Conference of Electron Devices and Solid-State Circuits

自引率

0.00%

发文量