采用40nm CMOS的50nA静态电流异步数字ldo，具有锁相环调制的快速dvs电源管理，具有5.6倍MIPS性能

2012 Symposium on VLSI Circuits (VLSIC) Pub Date : 2012-06-13 DOI:10.1109/VLSIC.2012.6243848

Yu-Huei Lee, S. Peng, A. C. Wu, Chao-Chang Chiu, Yao-Yi Yang, Ming-Hsin Huang, Ke-Horng Chen, Ying-Hsi Lin, Shih-Wei Wang, Ching-Yuan Yeh, Chen-Chih Huang, Chao-Cheng Lee

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引用次数: 13

摘要

结合锁相调制开关稳压器(SWR)的50nA静态电流异步数字ldo (DLDO)具有混合电源管理功能。本文提出的双向异步波管道(BAWP)在异步DLDO中实现了几十纳秒内的快速分布式交换机(F-DVS)操作。前置相位放大器的SWR实现了动态DVS和94%的峰值效率，并通过混合操作提高了5.6倍的MIPS性能。制作的芯片在40nm CMOS中占地1.04mm2。

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A 50nA quiescent current asynchronous digital-LDO with PLL-modulated fast-DVS power management in 40nm CMOS for 5.6 times MIPS performance

A 50nA quiescent current asynchronous digital-LDO (DLDO) integrated with the PLL-modulated switching regulator (SWR) exhibits the hybrid power management operation. The proposed bidirectional asynchronous wave pipeline (BAWP) in the asynchronous DLDO realizes the Fast-DVS (F-DVS) operation within tens of nano-seconds. The SWR with the leading phase amplifier achieves on-the-fly DVS and 94% peak efficiency, as well as improves 5.6 times MIPS performance through hybrid operation. The fabricated chip occupies 1.04mm2 in 40nm CMOS.

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2012 Symposium on VLSI Circuits (VLSIC)

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