A new 16-bit ALU using variable stage adder and PTL mux

ALU is an integral part of the processor. And it is also one of the highest power density location in the processor. Hence in order to optimize the performance of processor, it is important to optimize the ALU. In this paper, proposed ALU having 8 functions has been designed using optimized adder structure. Also, use of pass transistors based multiplexer reduces the transistor count to around 80%. The proposed 16-bit ALU is implemented using 90 nm CMOS technology in Cadence Virtuoso. The results shows improvement in delay by 23.48 % and power consumption has been reduced by 2.76 %. It is pertinent to mention that the delay improvement in the proposed circuits have been achieved without increase in any circuit complexity and power dissipation. The proposed circuits are suitable for low power and high speed VLSI based arithmetic circuits.