动态电流模式逻辑(Dynamic current mode logic, DyCML)是一种新型的低功耗高性能逻辑系列

Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044) Pub Date : 2000-05-21 DOI:10.1109/CICC.2000.852699

M. Allam, M. Elmasry

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引用次数: 18

摘要

本文提出了一种适用于低功耗高性能VLSI应用的新型逻辑样式DyCML。新的逻辑系列结合了MCML电路的速度，低电源电压和抗噪性优势，同时实现了动态电路的低待机电流和设计简单的特点。仿真结果表明，DyCML电路在功耗和时延方面都优于CMOS和DCVS逻辑电路。一个16位DyCML进位前置加法器(CLA)以0.6 /spl mu/m的速度制造，在400 MHz时功耗为21.2 mW，延迟为1.1 ns。

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Dynamic current mode logic (DyCML), a new low-power high-performance logic family

This paper presents a new logic style DyCML for low-power high-performance VLSI applications. The new logic family combines the speed, low supply voltage and noise immunity advantages of MCML circuits while achieving the low standby current and design simplicity features of dynamic circuits. Simulation results show that DyCML circuits are superior to CMOS and DCVS logic styles in terms of power and delay. A 16 bit DyCML Carry Look Ahead Adder (CLA) fabricated in 0.6 /spl mu/m achieves a delay of 1.1 ns while dissipating 21.2 mW at 400 MHz.

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Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)

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