A 10b Source-Driver IC with LSB-Stacked LV-to-HV-Amplify DAC Achieving 2688μm2/channel and 4.8mV DVO for Mobile OLED Displays

As the spatial resolution of mobile OLED displays increases, more than a thousand column channels must be integrated into a source-driver IC (SD-IC). Furthermore, the data resolution of the DAC occupying the majority area of the column channel must become higher for color-depth improvement. The top-left of Fig. 5.9.1 shows a typical SD-IC architecture composed of R-DAC-based column channels sharing a global resistor-string. The switch-array size of the conventional R-DAC increases proportionally to a power of 2 with DAC resolution. Moreover, since the full-scale range ${\left(FSR\,=\,V_{H}\,-\,V_{L}\right)}$ of the R-string is directly correlated with the dynamic range in an OLED display, the R-DAC, including level-shifters (L/S), must be implemented with high-voltage MOSFETs (HV-MOS). Accordingly, even modern CMOS technology nodes are still unable to shrink the SD-IC size considerably. Thus far, many efforts to improve the DAC area efficiency employing a voltage-interpolative sub-DAC have been reported [1 – 3], as shown in the top-middle of Fig. 5.9.1. However, the use of a 2-output HV R-dAc, which occupies 2× larger area, is mandatory for voltage interpolation. Mismatch between sub-DACs is also inevitable, and thus the inter-channel uniformity, one of the key performance metrics in a SD-IC, deteriorates significantly. This paper presents an ultra-compact-sized 10b SD-IC achieving an area of 2688μm2/nel even without adopting voltage-interpolation. As shown in the top-right of Fig. 5.9.1, two key innovations of this work include: 1) a mismatch-insensitive switched-capacitor-based LV-to-HV-amplify DAC, which enables an 8b R-DAC to be realized with only low-voltage MOSFETs (LV-MOS) while obtaining the HV output, and 2) a deviation-free 2b LSB stack-up (LSU) technique enabling finer resolution consuming little area. Considering a 1.5V thin-gate MOS is 24×smaller than a 5V thick-gate MOS for the same ${R_{\text{ON}}}$ in 130nm CMOS, this work can achieve dramatic shrinkage of the chip size due to the all-LV-MOS-based R-DAC in conjunction with the elimination of L/S. In addition, both our innovations are highly robust to process variations and thus contribute to overcoming inter-channel mismatch, which is a drawback of prior voltage-interpolative schemes.