40nm CMOS内部集成电路的核心芯片设计

2021 6th International Conference on Integrated Circuits and Microsystems (ICICM) Pub Date : 2021-10-22 DOI:10.1109/ICICM54364.2021.9660335

Shisong Wan, Lu Tang, Xuan Shen

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摘要

本文设计了一个I2C (Inter-Integrated Circuit)接口模块。I2C接口模块用于全数字锁相环(ADPLL)。I2C接口模块前端仿真频率为100MHz，采用主机输入、从机输出的设计。I2C接口模块基于40nm COMS工艺，共有55个输出引脚。

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The Core Chip Design of Inter-Integrated Circuit in 40nm CMOS

This paper designs an I2C (Inter-Integrated Circuit) interface module. The I2C interface module is used in all digital phase-locked loop (ADPLL). The front-end simulation frequency of the I2C interface module is 100MHz, and adopt the design of host input and output from the slave. The I2C interface module is based on 40nm COMS process and has a total of 55 output pins.

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2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)

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