带SAR ADC的无源单端差分变换器,实现6.1fJ/转换步长

Mariska van der Struijk, Kevin Pelzers, P. Harpe
{"title":"带SAR ADC的无源单端差分变换器,实现6.1fJ/转换步长","authors":"Mariska van der Struijk, Kevin Pelzers, P. Harpe","doi":"10.1109/MWSCAS47672.2021.9531821","DOIUrl":null,"url":null,"abstract":"This paper proposes a passive switched-capacitor single-ended-to-differential-converter (SDC) as a front-end of a differential SAR ADC to enable digitization of single-ended signals. Compared to active SDC solutions or single-ended SAR ADCs, the proposed solution offers the smallest total capacitance as well as best power efficiency and least chip area. A noise analysis further shows that the passive SDC does not result in a noise penalty of the overall system. A prototype implementation in 65nm CMOS achieves a figure-of-merit of 6.1fJ/conversion-step at 20MS/s, while reaching an SNDR of 54.7dB up to Nyquist and occupying a chip area of only 60µm × 36µm.","PeriodicalId":6792,"journal":{"name":"2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"16 1","pages":"288-291"},"PeriodicalIF":0.0000,"publicationDate":"2021-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"A Passive Single-Ended-to-Differential-Converter with SAR ADC Achieving 6.1fJ/Conversion-Step\",\"authors\":\"Mariska van der Struijk, Kevin Pelzers, P. Harpe\",\"doi\":\"10.1109/MWSCAS47672.2021.9531821\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper proposes a passive switched-capacitor single-ended-to-differential-converter (SDC) as a front-end of a differential SAR ADC to enable digitization of single-ended signals. Compared to active SDC solutions or single-ended SAR ADCs, the proposed solution offers the smallest total capacitance as well as best power efficiency and least chip area. A noise analysis further shows that the passive SDC does not result in a noise penalty of the overall system. A prototype implementation in 65nm CMOS achieves a figure-of-merit of 6.1fJ/conversion-step at 20MS/s, while reaching an SNDR of 54.7dB up to Nyquist and occupying a chip area of only 60µm × 36µm.\",\"PeriodicalId\":6792,\"journal\":{\"name\":\"2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)\",\"volume\":\"16 1\",\"pages\":\"288-291\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2021-08-09\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/MWSCAS47672.2021.9531821\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MWSCAS47672.2021.9531821","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1

摘要

本文提出了一种无源开关电容单端差分变换器(SDC)作为差分SAR ADC的前端,以实现单端信号的数字化。与有源SDC解决方案或单端SAR adc相比,该方案具有最小的总电容、最佳的功率效率和最小的芯片面积。噪声分析进一步表明,被动式SDC不会导致整个系统的噪声惩罚。在65nm CMOS中实现的原型实现在20MS/s下实现了6.1fJ/转换步长,SNDR达到54.7dB,且芯片面积仅为60 μ m × 36 μ m。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A Passive Single-Ended-to-Differential-Converter with SAR ADC Achieving 6.1fJ/Conversion-Step
This paper proposes a passive switched-capacitor single-ended-to-differential-converter (SDC) as a front-end of a differential SAR ADC to enable digitization of single-ended signals. Compared to active SDC solutions or single-ended SAR ADCs, the proposed solution offers the smallest total capacitance as well as best power efficiency and least chip area. A noise analysis further shows that the passive SDC does not result in a noise penalty of the overall system. A prototype implementation in 65nm CMOS achieves a figure-of-merit of 6.1fJ/conversion-step at 20MS/s, while reaching an SNDR of 54.7dB up to Nyquist and occupying a chip area of only 60µm × 36µm.
求助全文
通过发布文献求助,成功后即可免费获取论文全文。 去求助
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术官方微信