一种亚1v低差稳压器,改善了低功率数字系统的瞬态性能

Y. Jiang, Dong Wang, P. K. Chan
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引用次数: 2

摘要

本文提出了一种基于翻转电压跟随器(FVF)的低压无输出电容低差(OCL-LDO)稳压器。它包括一个瞬态增强推挽(TEPP)驱动级,以提高在低静态功率下的响应。通过简单的米勒补偿(SMC)和改进的阻尼因子控制(DFC)补偿,调节器允许小的补偿电容在不同负载条件下保持电路稳定性,同时增加设计灵活性。经UMC 65nm CMOS技术验证,该稳压器可支持100pf至3nf的容性负载。在0.9 V电源下,最大负载电流为10ma,压降电压为200mv,静态电流小于20 μA。在负载电流转换期间,稳压器的输出电压保持在最终稳态电压水平的1%以内。与已有报道的同类器件相比,它具有良好的暂态性能,特别适用于低功耗数字系统。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A sub-1V low dropout regulator with improved transient performance for low power digital systems
This paper presents a low-voltage Flipped Voltage Follower (FVF) based output-capacitorless low-dropout (OCL-LDO) regulator. It consists of a transient-enhanced push-pull (TEPP) driving stage to improve the response at low quiescent power. With simple Miller compensation (SMC) and modified damping factor control (DFC) compensation, the regulator permits small compensation capacitance for maintaining circuit stability under different loading conditions whilst increasing the design flexibility. Validated by UMC 65nm CMOS technology, the regulator can support the capacitive load from 100 pF to 3 nF. It delivers a maximum load current of 10 mA with a dropout voltage of 200 mV in 0.9 V supply and a quiescent current of less than 20 μA. The regulator's output voltage stays within 1% of the final steady-state voltage level during load current transitions. Compared with other reported counterparts, it displays reasonable good transient figure-of-merits (FOMs), particularly suitable for low power digital systems.
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