一种基于HDL的减小面积NOC路由器架构

2013 International Conference on Emerging Trends in VLSI, Embedded System, Nano Electronics and Telecommunication System (ICEVENT) Pub Date : 2013-04-11 DOI:10.1109/ICEVENT.2013.6496593

M. S. Suraj, D. Muralidharan, K. Seshu Kumar

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引用次数: 5

摘要

在这项工作中，我们提出了具有五端口支持的NOC路由器架构，该架构采用双交叉排排列，通过使用主导路由算法减少了由于双交叉排结构引起的延迟。这种安排更有效，减少了大约10%的设备利用率。

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A HDL based reduced area NOC router architecture

In this work, we present the NOC router architecture with five port support which utilizes dual crossbar arrangement, the latency which arises due to the dual cross bar architecture is reduced by using predominant routing algorithm. This arrangement is more efficient and reduces about 10 % of device utilization.

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来源期刊

2013 International Conference on Emerging Trends in VLSI, Embedded System, Nano Electronics and Telecommunication System (ICEVENT)

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