{"title":"减少组合电路的测试输入","authors":"B. Karimi, L. G. Johnson","doi":"10.1109/MWSCAS.1991.252073","DOIUrl":null,"url":null,"abstract":"For a given method of design for testability a mechanism is proposed to reduce the number of test inputs by connecting two or more test inputs together. It is shown that by preprocessing the reconvergent fanouts it is possible to identify and remove some of the redundant reconvergent paths. Reconvergent fanouts with multiple reconvergent gates are investigated, and their application in design for testability is discussed.<<ETX>>","PeriodicalId":6453,"journal":{"name":"[1991] Proceedings of the 34th Midwest Symposium on Circuits and Systems","volume":"8 1","pages":"874-878 vol.2"},"PeriodicalIF":0.0000,"publicationDate":"1991-05-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Reduction of test inputs for combinational circuits\",\"authors\":\"B. Karimi, L. G. Johnson\",\"doi\":\"10.1109/MWSCAS.1991.252073\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"For a given method of design for testability a mechanism is proposed to reduce the number of test inputs by connecting two or more test inputs together. It is shown that by preprocessing the reconvergent fanouts it is possible to identify and remove some of the redundant reconvergent paths. Reconvergent fanouts with multiple reconvergent gates are investigated, and their application in design for testability is discussed.<<ETX>>\",\"PeriodicalId\":6453,\"journal\":{\"name\":\"[1991] Proceedings of the 34th Midwest Symposium on Circuits and Systems\",\"volume\":\"8 1\",\"pages\":\"874-878 vol.2\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1991-05-14\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"[1991] Proceedings of the 34th Midwest Symposium on Circuits and Systems\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/MWSCAS.1991.252073\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"[1991] Proceedings of the 34th Midwest Symposium on Circuits and Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MWSCAS.1991.252073","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Reduction of test inputs for combinational circuits
For a given method of design for testability a mechanism is proposed to reduce the number of test inputs by connecting two or more test inputs together. It is shown that by preprocessing the reconvergent fanouts it is possible to identify and remove some of the redundant reconvergent paths. Reconvergent fanouts with multiple reconvergent gates are investigated, and their application in design for testability is discussed.<>