S. Gujare, Gaurav Jagtap, D. Gharpure, S. Ananthakrishnan
{"title":"基于FPGA的数据采集与分析系统","authors":"S. Gujare, Gaurav Jagtap, D. Gharpure, S. Ananthakrishnan","doi":"10.1109/ISPTS.2012.6260914","DOIUrl":null,"url":null,"abstract":"This paper presents prototype design of the FPGA based digital back-end for data acquisition and processing. The system consists of acquiring 1024 samples of data. The stored data is input to FFT core for data analysis. An RS 232 port has been implemented to aid in testing and debugging the system. Various modules are developed in VHDL and integrated to realize the complete system. The design is implemented and tested on SPARTAN 3E platform.","PeriodicalId":6431,"journal":{"name":"2012 1st International Symposium on Physics and Technology of Sensors (ISPTS-1)","volume":"180 1","pages":"177-180"},"PeriodicalIF":0.0000,"publicationDate":"2012-03-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":"{\"title\":\"FPGA based data acquisition and analysis system\",\"authors\":\"S. Gujare, Gaurav Jagtap, D. Gharpure, S. Ananthakrishnan\",\"doi\":\"10.1109/ISPTS.2012.6260914\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents prototype design of the FPGA based digital back-end for data acquisition and processing. The system consists of acquiring 1024 samples of data. The stored data is input to FFT core for data analysis. An RS 232 port has been implemented to aid in testing and debugging the system. Various modules are developed in VHDL and integrated to realize the complete system. The design is implemented and tested on SPARTAN 3E platform.\",\"PeriodicalId\":6431,\"journal\":{\"name\":\"2012 1st International Symposium on Physics and Technology of Sensors (ISPTS-1)\",\"volume\":\"180 1\",\"pages\":\"177-180\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2012-03-07\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"6\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2012 1st International Symposium on Physics and Technology of Sensors (ISPTS-1)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISPTS.2012.6260914\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2012 1st International Symposium on Physics and Technology of Sensors (ISPTS-1)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISPTS.2012.6260914","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
This paper presents prototype design of the FPGA based digital back-end for data acquisition and processing. The system consists of acquiring 1024 samples of data. The stored data is input to FFT core for data analysis. An RS 232 port has been implemented to aid in testing and debugging the system. Various modules are developed in VHDL and integrated to realize the complete system. The design is implemented and tested on SPARTAN 3E platform.