Extending the viability of I/sub DDQ/ testing in the deep submicron era

I/sub DDQ/ testing has become a widely accepted defect detection technique in CMOS ICs. However, its effectiveness in deep submicron is threatened by the increased transistor sub-threshold leakage current. In this paper, a new I/sub DDQ/ testing scheme is proposed. This scheme is based on the elimination, during I/sub DDQ/ testing, of the normal leakage current from the sensing node of the circuit under test so that already known in the open literature I/sub DDQ/ sensing techniques can be applied in deep submicron.