{"title":"具有锁存式比较器和动态开关电流方案的幅值到数字转换器","authors":"Hsin-Liang Chen, Yin-Qin Ye, Jen-Shiun Chiang","doi":"10.1109/IET-ICETA56553.2022.9971646","DOIUrl":null,"url":null,"abstract":"A magnitude to digital converter is proposed using a latch-type comparator to replace the conventional opamp-based comparator. The PVT-dependent timing error can be relieved by employing the latch-type comparator and rearranging the decision control circuits. Besides, the power efficiency can be improved within the low and high speed operations. For increasing the linearity of the converting process, a dynamic current source is also developed to obtain the best coefficient of determination. A prototype of 10-bit converter was designed to operate at 40-kS/s with only 56.S-$\\mu$W of power dissipations, respectively.","PeriodicalId":46240,"journal":{"name":"IET Networks","volume":null,"pages":null},"PeriodicalIF":1.3000,"publicationDate":"2022-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Magnitude to Digital Converter with Latch-Type Comparator and Dynamic Switching Current Scheme\",\"authors\":\"Hsin-Liang Chen, Yin-Qin Ye, Jen-Shiun Chiang\",\"doi\":\"10.1109/IET-ICETA56553.2022.9971646\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A magnitude to digital converter is proposed using a latch-type comparator to replace the conventional opamp-based comparator. The PVT-dependent timing error can be relieved by employing the latch-type comparator and rearranging the decision control circuits. Besides, the power efficiency can be improved within the low and high speed operations. For increasing the linearity of the converting process, a dynamic current source is also developed to obtain the best coefficient of determination. A prototype of 10-bit converter was designed to operate at 40-kS/s with only 56.S-$\\\\mu$W of power dissipations, respectively.\",\"PeriodicalId\":46240,\"journal\":{\"name\":\"IET Networks\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":1.3000,\"publicationDate\":\"2022-10-14\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IET Networks\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IET-ICETA56553.2022.9971646\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q3\",\"JCRName\":\"COMPUTER SCIENCE, INFORMATION SYSTEMS\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IET Networks","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IET-ICETA56553.2022.9971646","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"COMPUTER SCIENCE, INFORMATION SYSTEMS","Score":null,"Total":0}
Magnitude to Digital Converter with Latch-Type Comparator and Dynamic Switching Current Scheme
A magnitude to digital converter is proposed using a latch-type comparator to replace the conventional opamp-based comparator. The PVT-dependent timing error can be relieved by employing the latch-type comparator and rearranging the decision control circuits. Besides, the power efficiency can be improved within the low and high speed operations. For increasing the linearity of the converting process, a dynamic current source is also developed to obtain the best coefficient of determination. A prototype of 10-bit converter was designed to operate at 40-kS/s with only 56.S-$\mu$W of power dissipations, respectively.
IET NetworksCOMPUTER SCIENCE, INFORMATION SYSTEMS-
CiteScore
5.00
自引率
0.00%
发文量
41
审稿时长
33 weeks
期刊介绍:
IET Networks covers the fundamental developments and advancing methodologies to achieve higher performance, optimized and dependable future networks. IET Networks is particularly interested in new ideas and superior solutions to the known and arising technological development bottlenecks at all levels of networking such as topologies, protocols, routing, relaying and resource-allocation for more efficient and more reliable provision of network services. Topics include, but are not limited to: Network Architecture, Design and Planning, Network Protocol, Software, Analysis, Simulation and Experiment, Network Technologies, Applications and Services, Network Security, Operation and Management.