基于45nm SOI CMOS的17.3 dBm输出功率和25% PAE的宽带毫米波差分叠加场效应晶体管功率放大器

J. Xia, A. Chung, S. Boumaiza
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引用次数: 11

摘要

本文提出了一种利用45纳米绝缘体上硅(SOI) CMOS技术的叠加场效应晶体管,设计一种高效的两级m毫米波功率放大器(PA)。它强调了在毫米频率(例如60GHz)设计单端多级放大器时遇到的两个主要问题,即对地寄生电感的重要来源和低频振荡的脆弱性。两级差分PA包括输入、级间和输出匹配网络,使用具有高耦合系数和低插入损耗的RF变压器实现。PA演示器显示了相当于12GHz (55-67GHz)的3db带宽。小信号增益、峰值功率附加效率和峰值输出功率分别为14.5dB、25%和17.3dBm。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A wideband millimeter-wave differential stacked-FET power amplifier with 17.3 dBm output power and 25% PAE in 45nm SOI CMOS
This paper presents the design of an efficient two-stage m illim eter-wave power amplifier (PA) using stacked field-effect transistors in 45nm silicon-on-insulator (SOI) CMOS technology. It highlights two major issues encountered when designing single-ended multistage PAs at millimeter frequencies (e.g., 60GHz), namely the significant source to ground parasitic inductance and the vulnerability to oscillation at low frequencies. The two-stage differential PA includes input, inter-stage and output matching networks implemented using RF transformers with a high coupling factor and reduced insertion losses. The PA demonstrator showed a 3-dB bandwidth equal to 12GHz (55–67GHz). The small signal gain, peak power added efficiency and peak output power were recorded as 14.5dB, 25% and 17.3dBm, respectively.
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