D. Fainstein, S. Rosenblatt, A. Cestero, N. Robson, T. Kirihata, S. Iyer
{"title":"动态内禀芯片ID采用32nm高k /金属栅极SOI嵌入式DRAM","authors":"D. Fainstein, S. Rosenblatt, A. Cestero, N. Robson, T. Kirihata, S. Iyer","doi":"10.1109/VLSIC.2012.6243832","DOIUrl":null,"url":null,"abstract":"A random intrinsic chip ID method generates a pair of 4Kb binary strings using retention fails in 32nm SOI embedded DRAM. Hardware results show ID overlap distance mean=0.58 and σ=0.76 and demonstrate 100% authentication for 346 chips. The analytical model predicts >; 99.999% unique IDs for 106 parts.","PeriodicalId":6347,"journal":{"name":"2012 Symposium on VLSI Circuits (VLSIC)","volume":"362 1","pages":"146-147"},"PeriodicalIF":0.0000,"publicationDate":"2012-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"11","resultStr":"{\"title\":\"Dynamic intrinsic chip ID using 32nm high-K/metal gate SOI embedded DRAM\",\"authors\":\"D. Fainstein, S. Rosenblatt, A. Cestero, N. Robson, T. Kirihata, S. Iyer\",\"doi\":\"10.1109/VLSIC.2012.6243832\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A random intrinsic chip ID method generates a pair of 4Kb binary strings using retention fails in 32nm SOI embedded DRAM. Hardware results show ID overlap distance mean=0.58 and σ=0.76 and demonstrate 100% authentication for 346 chips. The analytical model predicts >; 99.999% unique IDs for 106 parts.\",\"PeriodicalId\":6347,\"journal\":{\"name\":\"2012 Symposium on VLSI Circuits (VLSIC)\",\"volume\":\"362 1\",\"pages\":\"146-147\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2012-06-13\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"11\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2012 Symposium on VLSI Circuits (VLSIC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIC.2012.6243832\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2012 Symposium on VLSI Circuits (VLSIC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.2012.6243832","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Dynamic intrinsic chip ID using 32nm high-K/metal gate SOI embedded DRAM
A random intrinsic chip ID method generates a pair of 4Kb binary strings using retention fails in 32nm SOI embedded DRAM. Hardware results show ID overlap distance mean=0.58 and σ=0.76 and demonstrate 100% authentication for 346 chips. The analytical model predicts >; 99.999% unique IDs for 106 parts.