{"title":"在神经形态模拟VLSI中,脉冲时序依赖的可塑性能否补偿过程失配?","authors":"K. Cameron, A. Murray","doi":"10.1109/ISCAS.2004.1329916","DOIUrl":null,"url":null,"abstract":"Analogue VLSI can be used to implement spike timing dependent neuromorphic training algorithms. This work presents a circuitry that uses spike timing to \"adapt out\" the effects of device mismatch in such circuits. Simulation results for the circuit implemented in 0.35 /spl mu/m CMOS process are reported.","PeriodicalId":6445,"journal":{"name":"2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)","volume":"6 1","pages":"V-V"},"PeriodicalIF":0.0000,"publicationDate":"2004-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"Can spike timing dependent plasticity compensate for process mismatch in neuromorphic analogue VLSI?\",\"authors\":\"K. Cameron, A. Murray\",\"doi\":\"10.1109/ISCAS.2004.1329916\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Analogue VLSI can be used to implement spike timing dependent neuromorphic training algorithms. This work presents a circuitry that uses spike timing to \\\"adapt out\\\" the effects of device mismatch in such circuits. Simulation results for the circuit implemented in 0.35 /spl mu/m CMOS process are reported.\",\"PeriodicalId\":6445,\"journal\":{\"name\":\"2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)\",\"volume\":\"6 1\",\"pages\":\"V-V\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2004-05-23\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISCAS.2004.1329916\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISCAS.2004.1329916","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Can spike timing dependent plasticity compensate for process mismatch in neuromorphic analogue VLSI?
Analogue VLSI can be used to implement spike timing dependent neuromorphic training algorithms. This work presents a circuitry that uses spike timing to "adapt out" the effects of device mismatch in such circuits. Simulation results for the circuit implemented in 0.35 /spl mu/m CMOS process are reported.