{"title":"一种基于65nm CMOS的28 ghz电流模反缺相功率放大器","authors":"Liang-Hui Li, Dongliang Ni, Jiazheng Chen, Jiwei Huang","doi":"10.1109/ICICM54364.2021.9660333","DOIUrl":null,"url":null,"abstract":"In this paper, a 28-GHz high efficiency outphasing power amplifier (PA) with Chireix compensation in 65-nm Silicon-On-Insulator (SOI) CMOS technology is proposed. To improve the power-back-off (PBO) efficiency, the PA uses a current-mode inverse outphasing architecture, which supports compatibility with current-mode PAs, highly efficient active load modulation. Meanwhile, the neutralization capacitor and source degeneration inductor technology is employed to tradeoff linearity and high efficiency requirements. At 28GHz with a supply voltage of 2.5/1.2V, the complete outphasing PA achieves a simulated saturated output power of 23.8dBm with 45.1% power-added efficiency (PAE) and 6dB back-off PAE of 25.2%, 1-dB compression output power of 21.8dBm, and gain of 16.6dB. The simulation results also show that the PA is unconditionally stable in the whole working frequency band. The power amplifier has a layout size of 1.02 mm2 and a core area of 0.46 mm2.","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"34 1","pages":"268-271"},"PeriodicalIF":0.0000,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A 28-GHz Current-Mode Inverse-Outphasing Power Amplifier in 65-nm CMOS\",\"authors\":\"Liang-Hui Li, Dongliang Ni, Jiazheng Chen, Jiwei Huang\",\"doi\":\"10.1109/ICICM54364.2021.9660333\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, a 28-GHz high efficiency outphasing power amplifier (PA) with Chireix compensation in 65-nm Silicon-On-Insulator (SOI) CMOS technology is proposed. To improve the power-back-off (PBO) efficiency, the PA uses a current-mode inverse outphasing architecture, which supports compatibility with current-mode PAs, highly efficient active load modulation. Meanwhile, the neutralization capacitor and source degeneration inductor technology is employed to tradeoff linearity and high efficiency requirements. At 28GHz with a supply voltage of 2.5/1.2V, the complete outphasing PA achieves a simulated saturated output power of 23.8dBm with 45.1% power-added efficiency (PAE) and 6dB back-off PAE of 25.2%, 1-dB compression output power of 21.8dBm, and gain of 16.6dB. The simulation results also show that the PA is unconditionally stable in the whole working frequency band. The power amplifier has a layout size of 1.02 mm2 and a core area of 0.46 mm2.\",\"PeriodicalId\":6693,\"journal\":{\"name\":\"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)\",\"volume\":\"34 1\",\"pages\":\"268-271\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2021-10-22\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICICM54364.2021.9660333\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICICM54364.2021.9660333","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 28-GHz Current-Mode Inverse-Outphasing Power Amplifier in 65-nm CMOS
In this paper, a 28-GHz high efficiency outphasing power amplifier (PA) with Chireix compensation in 65-nm Silicon-On-Insulator (SOI) CMOS technology is proposed. To improve the power-back-off (PBO) efficiency, the PA uses a current-mode inverse outphasing architecture, which supports compatibility with current-mode PAs, highly efficient active load modulation. Meanwhile, the neutralization capacitor and source degeneration inductor technology is employed to tradeoff linearity and high efficiency requirements. At 28GHz with a supply voltage of 2.5/1.2V, the complete outphasing PA achieves a simulated saturated output power of 23.8dBm with 45.1% power-added efficiency (PAE) and 6dB back-off PAE of 25.2%, 1-dB compression output power of 21.8dBm, and gain of 16.6dB. The simulation results also show that the PA is unconditionally stable in the whole working frequency band. The power amplifier has a layout size of 1.02 mm2 and a core area of 0.46 mm2.
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