{"title":"基于STI的LDMOS新型栅极结构设计","authors":"Ziquan Fang, Zhaozhao Xu, W. Qian","doi":"10.1109/CSTIC49141.2020.9282385","DOIUrl":null,"url":null,"abstract":"Conventional STI based LDMOS devices always have an extended gate which performs as a poly plate on top of the STI. In this paper, we have proposed a novel LDMOS gate architecture with no overlap between gate and STI. Instead, the contacts landing on the STI perform as plate to obtain high off-state breakdown voltage (offBV). The novel LDMOS is compatible with CMOS process, and the offBV can be above 20V without additional drift implant mask. TCAD simulation is used to explain the underlying physics of the proposed novel architecture.","PeriodicalId":6848,"journal":{"name":"2020 China Semiconductor Technology International Conference (CSTIC)","volume":"51 1","pages":"1-3"},"PeriodicalIF":0.0000,"publicationDate":"2020-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A Novel Gate Architecture Design in STI Based LDMOS\",\"authors\":\"Ziquan Fang, Zhaozhao Xu, W. Qian\",\"doi\":\"10.1109/CSTIC49141.2020.9282385\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Conventional STI based LDMOS devices always have an extended gate which performs as a poly plate on top of the STI. In this paper, we have proposed a novel LDMOS gate architecture with no overlap between gate and STI. Instead, the contacts landing on the STI perform as plate to obtain high off-state breakdown voltage (offBV). The novel LDMOS is compatible with CMOS process, and the offBV can be above 20V without additional drift implant mask. TCAD simulation is used to explain the underlying physics of the proposed novel architecture.\",\"PeriodicalId\":6848,\"journal\":{\"name\":\"2020 China Semiconductor Technology International Conference (CSTIC)\",\"volume\":\"51 1\",\"pages\":\"1-3\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2020-06-26\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2020 China Semiconductor Technology International Conference (CSTIC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/CSTIC49141.2020.9282385\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2020 China Semiconductor Technology International Conference (CSTIC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CSTIC49141.2020.9282385","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A Novel Gate Architecture Design in STI Based LDMOS
Conventional STI based LDMOS devices always have an extended gate which performs as a poly plate on top of the STI. In this paper, we have proposed a novel LDMOS gate architecture with no overlap between gate and STI. Instead, the contacts landing on the STI perform as plate to obtain high off-state breakdown voltage (offBV). The novel LDMOS is compatible with CMOS process, and the offBV can be above 20V without additional drift implant mask. TCAD simulation is used to explain the underlying physics of the proposed novel architecture.
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