50MS/s 80dB SFDR数字校准流水线ADC与工作负载平衡的MDAC

2011 IEEE International Conference of Electron Devices and Solid-State Circuits Pub Date : 2011-12-29 DOI:10.1109/EDSSC.2011.6117737

Yajie Qin, Qihui Chen, S. Signed, Zhiliang Hong

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引用次数: 0

摘要

提出了一种工作负载平衡乘法数模转换器(WB-MDAC)，以提高多位流水线级的求解效率，并在一个14位50 ms /s数字校准流水线ADC中进行了验证。该ADC采用0.13µm 1P8M CMOS技术，包括内部参考缓冲器，其有效面积为1.3 mm2。它从1.2 v电源消耗76mW，实现64.4 dB SNDR和超过80 dB SFDR。

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A 50MS/s 80dB SFDR digital calibrated pipelined ADC with workload-balanced MDAC

A workload-balanced multiplying digital-to-analog converter (WB-MDAC) is proposed to improve the settling efficiency of multi-bit pipeline stages, and demonstrated in a 14-bit 50-MS/s digital calibrated pipelined ADC. The presented ADC occupies an active area of 1.3 mm2 in 0.13-µm 1P8M CMOS technology, including internal reference buffers. It dissipates 76mW from a 1.2-V supply, and achieves 64.4 dB SNDR and over 80 dB SFDR.

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2011 IEEE International Conference of Electron Devices and Solid-State Circuits

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