{"title":"第28部分概述:混合adc","authors":"Tai-Cheng Lee, B. Verbruggen, U. Moon","doi":"10.1109/ISSCC.2017.7870462","DOIUrl":null,"url":null,"abstract":"Analog-to-digital converters (ADCs) continue to evolve from classical architectures into hybrid converters that combine the strengths of various ADC types. This session demonstrates multiple hybrid ADCs ranging from MHz to GHz bandwidths, employing combinations of SAR, pipeline and oversampling architectures. Pipelined-SAR ADCs utilizing PVT-stabilized dynamic amplifiers, separate comparators per decision and digital amplifiers are disclosed. Noise-shaping phase-domain excess-loop-delay compensation as well as a double noise-shaping quantizer are employed in the ADCs to improve the conversion efficiency.","PeriodicalId":6511,"journal":{"name":"2016 IEEE International Solid-State Circuits Conference (ISSCC)","volume":"36 1","pages":"464-465"},"PeriodicalIF":0.0000,"publicationDate":"2017-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Session 28 overview: Hybrid ADCs\",\"authors\":\"Tai-Cheng Lee, B. Verbruggen, U. Moon\",\"doi\":\"10.1109/ISSCC.2017.7870462\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Analog-to-digital converters (ADCs) continue to evolve from classical architectures into hybrid converters that combine the strengths of various ADC types. This session demonstrates multiple hybrid ADCs ranging from MHz to GHz bandwidths, employing combinations of SAR, pipeline and oversampling architectures. Pipelined-SAR ADCs utilizing PVT-stabilized dynamic amplifiers, separate comparators per decision and digital amplifiers are disclosed. Noise-shaping phase-domain excess-loop-delay compensation as well as a double noise-shaping quantizer are employed in the ADCs to improve the conversion efficiency.\",\"PeriodicalId\":6511,\"journal\":{\"name\":\"2016 IEEE International Solid-State Circuits Conference (ISSCC)\",\"volume\":\"36 1\",\"pages\":\"464-465\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2017-02-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2016 IEEE International Solid-State Circuits Conference (ISSCC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISSCC.2017.7870462\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 IEEE International Solid-State Circuits Conference (ISSCC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC.2017.7870462","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Analog-to-digital converters (ADCs) continue to evolve from classical architectures into hybrid converters that combine the strengths of various ADC types. This session demonstrates multiple hybrid ADCs ranging from MHz to GHz bandwidths, employing combinations of SAR, pipeline and oversampling architectures. Pipelined-SAR ADCs utilizing PVT-stabilized dynamic amplifiers, separate comparators per decision and digital amplifiers are disclosed. Noise-shaping phase-domain excess-loop-delay compensation as well as a double noise-shaping quantizer are employed in the ADCs to improve the conversion efficiency.