一种用于具有互补门源驱动的触发器的高速50%节能半摆时钟方案

ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361) Pub Date : 1999-10-26 DOI:10.1109/ICVC.1999.821004

Jin-Cheon Kim, Sanghoon Lee, Hong-June Park

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引用次数: 2

摘要

提出了一种门源驱动互补的CMOS触发器半摆幅时钟方案，使时钟系统功耗降低43%，同时保持触发器延迟时间与传统的全摆幅时钟方案相同。采用该方案的前半级触发器的延迟时间比采用前半摆时钟方案的延迟时间少一半。

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A high-speed 50% power-saving half-swing clocking scheme for flip-flop with complementary gate and source drive

A half-swing clocking scheme with a complementary gate and source drive was proposed for CMOS flip-flop to reduce the power consumption of the clock system by 43%, while keeping the flip-flop delay time to be the same as that of the conventional full-swing clocking scheme. The delay time of the preceding half stage of flip-flop using this scheme is less than half that using the previous half-swing clocking scheme.

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来源期刊

ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361)

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