FFT剪枝算法在FPGA上的设计与实现

2017 7th International Conference on Cloud Computing, Data Science & Engineering - Confluence Pub Date : 2017-01-01 DOI:10.1109/CONFLUENCE.2017.7943248

C. V. Kumar, K. Sastry

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引用次数: 4

摘要

数字信号处理(DSP)已成为电子技术进步的一个重要组成部分。在所有的DSP操作中，快速傅里叶变换(FFT)在信号处理中起着突出的作用。由于不必要的Z计算，当零值输入(Z)的数量超过非零值输入(NZ)时，FFT的计算时间会减少。上述问题可以通过FFT中的Pruning (Partial, Complete)方法最小化Ζ上的计算来解决。在硬件上实现了剪枝方法，计算时间得到了改善。FFT修剪是在Verilog中开发的，并在Spartan 3E FPGA (xc3s500e-fg320-5)上进行了验证。

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Design and implementation of FFT pruning algorithm on FPGA

Digital Signal Processing (DSP) has evolved as an integrated component in electronics advancement. Among all the DSP operations, Fast Fourier Transform (FFT) plays a prominent role in signal processing. FFT computational time reduces when the number of zero valued inputs (Z) outnumbers the non-zero valued inputs (NZ) due to unnecessary computations for Z. The above issue can be resolved by minimizing computations on Ζ by the method Pruning (Partial, Complete) in FFT. The pruning method is implemented in the hardware and computational time improvement is observed. The FFT Pruning is developed in Verilog and validated on Spartan 3E FPGA (xc3s500e-fg320-5).

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2017 7th International Conference on Cloud Computing, Data Science & Engineering - Confluence

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