{"title":"一种新颖的低功耗低复杂度芯片解决方案,用于CMOS 0.18µm技术的可调谐UWB发射机","authors":"M. Zhao, B. Li, Z. H. Wu","doi":"10.1109/EDSSC.2011.6117634","DOIUrl":null,"url":null,"abstract":"In this paper, a novel UWB transmitter chip is proposed, based on the 0.18 µm CMOS technology. A novel transmitting solution is adopted to realize a low-power and low-complexity physical implementation for future high data rate wireless component interconnect and implantable electronic applications. A UWB PA with standby, a digital ring on-off VCO, a subtractor for eliminating base-band component from the output of the VCO, and a narrow pulse generator are employed to achieve the chip with the maximum data-rate of 200Mbps, tunable-band of licensed 3∼7GHz, low-power of 8pJ/bit, and a small circuit area of 0.2mm2, of which the proposed subtractor, VCO, and PA play the important roles in reducing power dissipation. The simulation results verify that the proposed design is suitable for future potential applications.","PeriodicalId":6363,"journal":{"name":"2011 IEEE International Conference of Electron Devices and Solid-State Circuits","volume":"445 1","pages":"1-2"},"PeriodicalIF":0.0000,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"A novel low-power low-complexity chip solution for tunable UWB transmitter in CMOS 0.18µm technology\",\"authors\":\"M. Zhao, B. Li, Z. H. Wu\",\"doi\":\"10.1109/EDSSC.2011.6117634\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, a novel UWB transmitter chip is proposed, based on the 0.18 µm CMOS technology. A novel transmitting solution is adopted to realize a low-power and low-complexity physical implementation for future high data rate wireless component interconnect and implantable electronic applications. A UWB PA with standby, a digital ring on-off VCO, a subtractor for eliminating base-band component from the output of the VCO, and a narrow pulse generator are employed to achieve the chip with the maximum data-rate of 200Mbps, tunable-band of licensed 3∼7GHz, low-power of 8pJ/bit, and a small circuit area of 0.2mm2, of which the proposed subtractor, VCO, and PA play the important roles in reducing power dissipation. The simulation results verify that the proposed design is suitable for future potential applications.\",\"PeriodicalId\":6363,\"journal\":{\"name\":\"2011 IEEE International Conference of Electron Devices and Solid-State Circuits\",\"volume\":\"445 1\",\"pages\":\"1-2\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2011-12-29\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2011 IEEE International Conference of Electron Devices and Solid-State Circuits\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EDSSC.2011.6117634\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2011 IEEE International Conference of Electron Devices and Solid-State Circuits","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EDSSC.2011.6117634","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A novel low-power low-complexity chip solution for tunable UWB transmitter in CMOS 0.18µm technology
In this paper, a novel UWB transmitter chip is proposed, based on the 0.18 µm CMOS technology. A novel transmitting solution is adopted to realize a low-power and low-complexity physical implementation for future high data rate wireless component interconnect and implantable electronic applications. A UWB PA with standby, a digital ring on-off VCO, a subtractor for eliminating base-band component from the output of the VCO, and a narrow pulse generator are employed to achieve the chip with the maximum data-rate of 200Mbps, tunable-band of licensed 3∼7GHz, low-power of 8pJ/bit, and a small circuit area of 0.2mm2, of which the proposed subtractor, VCO, and PA play the important roles in reducing power dissipation. The simulation results verify that the proposed design is suitable for future potential applications.